Design of High Performance Single-Port 5T SRAM Cell with Reduced Leakage Current

In this paper, a novel single-port five-transistor (5T) Static Random Access Memory (SRAM) cell and associated read/write assist are proposed. Amongst them, a word line suppression circuit is to provide a voltage of the respective connected word line to be lower than or equal to the power supply voltage VDD, so that the read/write-ability of the cell can be improved, and the half-selected cells disturbance can be reduced. Furthermore, a voltage control circuit is coupled to the sources corresponding to the driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. In addition, a pre-charging circuit is designed to pull up the bit line BL of a selected column to the voltage VDD before the read operation. Finally, with the standby start-up circuit design, the memory cell can be rapidly switched to the standby mode, thereby reducing leakage current in standby.